cpldfit: version K.39 Xilinx Inc. Fitter Report Design Name: main Date: 4- 8-2009, 3:38PM Device Used: XC9572XL-10-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 50 /72 ( 69%) 152 /360 ( 42%) 75 /216 ( 35%) 26 /72 ( 36%) 15 /34 ( 44%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 17/18 21/54 50/90 3/ 9 FB2 11/18 21/54 27/90 5/ 9 FB3 4/18 12/54 11/90 0/ 9 FB4 18/18* 21/54 64/90 7/ 7* ----- ----- ----- ----- 50/72 75/216 152/360 15/34 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK_SLOW' mapped onto global clock net GCK2. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 3 3 | I/O : 13 28 Output : 11 11 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 15 15 ** Power Data ** There are 50 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 11 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State LED<0> 2 4 FB1_2 1~ I/O O STD SLOW SET LED<1> 2 5 FB1_5 2~ I/O O STD SLOW SET EN_DISP<1> 2 2 FB2_5 36~ I/O O STD FAST SET EN_DISP<0> 1 1 FB2_6 37~ I/O O STD FAST RESET G 2 4 FB4_2 25~ I/O O STD SLOW D 4 4 FB4_5 26~ I/O O STD SLOW C 3 4 FB4_8 27~ I/O O STD SLOW F 4 4 FB4_11 28~ I/O O STD SLOW E 3 4 FB4_14 29~ I/O O STD SLOW B 5 4 FB4_15 33~ I/O O STD SLOW A 4 4 FB4_17 34~ I/O O STD SLOW ** 39 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State accu_in<5>/accu_in<5>_CE 1 3 FB1_1 STD XLXN_163 1 1 FB1_3 STD RESET $OpTx$FX_DC$9 1 3 FB1_4 STD $OpTx$FX_DC$12 1 4 FB1_6 STD accu_out<0> 3 4 FB1_7 STD RESET accu_in<7> 3 5 FB1_8 STD RESET accu_in<6> 3 5 FB1_9 STD RESET accu_in<5> 3 5 FB1_10 STD RESET accu_in<4> 3 5 FB1_11 STD RESET cnt<2> 4 5 FB1_12 STD RESET cnt<0> 4 5 FB1_13 STD RESET accu_out<6> 4 5 FB1_14 STD RESET accu_out<5> 4 5 FB1_15 STD RESET cnt<1> 5 8 FB1_16 STD RESET accu_out<7> 6 7 FB1_17 STD RESET XLXN_204 1 1 FB2_10 STD RESET $OpTx$FX_DC$7 1 4 FB2_11 STD $OpTx$FX_DC$6 1 4 FB2_12 STD XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D 2 2 FB2_13 STD cnt<3> 3 4 FB2_14 STD RESET d3/d3_D2 4 6 FB2_15 STD d2/d2_D2 4 6 FB2_16 STD accu_in<3> 4 5 FB2_17 STD RESET $OpTx$FX_DC$3 4 6 FB2_18 STD XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D 2 2 FB3_15 STD XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D 2 2 FB3_16 STD XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2 3 3 FB3_17 STD XLXN_307/XLXN_307_D2 4 6 FB3_18 STD $OpTx$FX_DC$11 1 4 FB4_1 STD accu_in<0> 3 4 FB4_3 STD RESET XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2 3 4 FB4_4 STD XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2 3 3 FB4_6 STD XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2 3 6 FB4_7 STD accu_out<3> 4 5 FB4_9 STD RESET accu_out<2> 4 5 FB4_10 STD RESET accu_in<2> 4 6 FB4_12 STD RESET accu_in<1> 4 5 FB4_13 STD RESET accu_out<4> 5 7 FB4_16 STD RESET accu_out<1> 5 7 FB4_18 STD RESET ** 4 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK_SLOW FB1_11 6~ GCK/I/O GCK TASTER_RES FB2_8 38~ I/O I TASTER_R FB2_9 39~ GSR/I/O I TASTER_U FB2_15 43~ I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 21/33 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use accu_in<5>/accu_in<5>_CE 1 0 0 4 FB1_1 (b) (b) LED<0> 2 0 0 3 FB1_2 1~ I/O O XLXN_163 1 0 0 4 FB1_3 (b) (b) $OpTx$FX_DC$9 1 0 0 4 FB1_4 (b) (b) LED<1> 2 0 0 3 FB1_5 2~ I/O O $OpTx$FX_DC$12 1 0 0 4 FB1_6 3 I/O (b) accu_out<0> 3 0 0 2 FB1_7 (b) (b) accu_in<7> 3 0 0 2 FB1_8 4 I/O (b) accu_in<6> 3 0 0 2 FB1_9 5 GCK/I/O (b) accu_in<5> 3 0 0 2 FB1_10 (b) (b) accu_in<4> 3 0 0 2 FB1_11 6 GCK/I/O GCK cnt<2> 4 0 0 1 FB1_12 (b) (b) cnt<0> 4 0 0 1 FB1_13 (b) (b) accu_out<6> 4 0 0 1 FB1_14 7 GCK/I/O (b) accu_out<5> 4 0 0 1 FB1_15 8 I/O (b) cnt<1> 5 0 0 0 FB1_16 (b) (b) accu_out<7> 6 1<- 0 0 FB1_17 9 I/O (b) (unused) 0 0 /\1 4 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$6 8: XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2 15: accu_in<5>/accu_in<5>_CE 2: $OpTx$FX_DC$9 9: XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2 16: accu_in<6> 3: LED<0> 10: XLXN_163 17: accu_out<6> 4: LED<1> 11: accu_in<0> 18: cnt<0> 5: TASTER_RES 12: accu_in<3> 19: cnt<1> 6: TASTER_R 13: accu_in<4> 20: cnt<2> 7: XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D 14: accu_in<5> 21: cnt<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs accu_in<5>/accu_in<5>_CE ...X.X...X.............................. 3 LED<0> ....XX...X....X......................... 4 XLXN_163 .....X.................................. 1 $OpTx$FX_DC$9 X................XX..................... 3 LED<1> ..XXXX...X.............................. 5 $OpTx$FX_DC$12 X................XXX.................... 4 accu_out<0> ....X.....X...X..X...................... 4 accu_in<7> ...XXX...X.....X........................ 5 accu_in<6> ...XXX...X...X.......................... 5 accu_in<5> ...XXX...X..X........................... 5 accu_in<4> ...XXX...X.X............................ 5 cnt<2> .X..X.........X....XX................... 5 cnt<0> X...X.........X..XX..................... 5 accu_out<6> ....X...X.....XX.X...................... 5 accu_out<5> ....X..X.....XX..X...................... 5 cnt<1> XX.XX.........X..XXX.................... 8 accu_out<7> ....X.X.X.....XXXX...................... 7 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 21/33 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 35 I/O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) EN_DISP<1> 2 0 0 3 FB2_5 36~ I/O O EN_DISP<0> 1 0 0 4 FB2_6 37~ I/O O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 38 I/O I (unused) 0 0 0 5 FB2_9 39 GSR/I/O I XLXN_204 1 0 0 4 FB2_10 (b) (b) $OpTx$FX_DC$7 1 0 0 4 FB2_11 40 GTS/I/O (b) $OpTx$FX_DC$6 1 0 0 4 FB2_12 (b) (b) XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D 2 0 0 3 FB2_13 (b) (b) cnt<3> 3 0 0 2 FB2_14 42 GTS/I/O (b) d3/d3_D2 4 0 0 1 FB2_15 43 I/O I d2/d2_D2 4 0 0 1 FB2_16 (b) (b) accu_in<3> 4 0 0 1 FB2_17 44 I/O (b) $OpTx$FX_DC$3 4 0 0 1 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$11 8: XLXN_204 15: accu_out<3> 2: $OpTx$FX_DC$12 9: accu_in<0> 16: accu_out<4> 3: EN_DISP<0> 10: accu_in<2> 17: accu_out<6> 4: LED<0> 11: accu_in<3> 18: accu_out<7> 5: LED<1> 12: accu_in<5>/accu_in<5>_CE 19: cnt<0> 6: TASTER_RES 13: accu_out<0> 20: cnt<2> 7: TASTER_U 14: accu_out<2> 21: cnt<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs EN_DISP<1> ..X..X.................................. 2 EN_DISP<0> .....X.................................. 1 XLXN_204 ......X................................. 1 $OpTx$FX_DC$7 ...XX.XX................................ 4 $OpTx$FX_DC$6 ...XX.XX................................ 4 XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D ..........X...X......................... 2 cnt<3> .X...X.....X........X................... 4 d3/d3_D2 ..X.X.....X...X..X..X................... 6 d2/d2_D2 ..X.X....X...X..X..X.................... 6 accu_in<3> X....X...XXX............................ 5 $OpTx$FX_DC$3 ..X.X...X...X..X..X..................... 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 12/42 Number of signals used by logic mapping into function block: 12 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 11 I/O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 12 I/O (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 13 I/O (unused) 0 0 0 5 FB3_9 14 I/O (unused) 0 0 0 5 FB3_10 (b) (unused) 0 0 0 5 FB3_11 18 I/O (unused) 0 0 0 5 FB3_12 (b) (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 19 I/O XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D 2 0 0 3 FB3_15 20 I/O (b) XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D 2 0 0 3 FB3_16 24 I/O (b) XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2 3 0 0 2 FB3_17 22 I/O (b) XLXN_307/XLXN_307_D2 4 0 0 1 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: EN_DISP<0> 5: accu_in<4> 9: accu_out<4> 2: LED<1> 6: accu_in<5> 10: accu_out<5> 3: XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2 7: accu_in<7> 11: accu_out<7> 4: accu_in<1> 8: accu_out<1> 12: cnt<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D ......X...X............................. 2 XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D ....X...X............................... 2 XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2 ..X..X...X.............................. 3 XLXN_307/XLXN_307_D2 XX.X...X.X.X............................ 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 21/33 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$FX_DC$11 1 0 0 4 FB4_1 (b) (b) G 2 0 0 3 FB4_2 25~ I/O O accu_in<0> 3 0 0 2 FB4_3 (b) (b) XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2 3 0 0 2 FB4_4 (b) (b) D 4 0 0 1 FB4_5 26~ I/O O XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2 3 0 0 2 FB4_6 (b) (b) XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2 3 0 0 2 FB4_7 (b) (b) C 3 0 0 2 FB4_8 27~ I/O O accu_out<3> 4 0 0 1 FB4_9 (b) (b) accu_out<2> 4 0 0 1 FB4_10 (b) (b) F 4 0 0 1 FB4_11 28~ I/O O accu_in<2> 4 0 0 1 FB4_12 (b) (b) accu_in<1> 4 0 0 1 FB4_13 (b) (b) E 3 0 0 2 FB4_14 29~ I/O O B 5 0 0 0 FB4_15 33~ I/O O accu_out<4> 5 0 0 0 FB4_16 (b) (b) A 4 0 0 1 FB4_17 34~ I/O O accu_out<1> 5 0 0 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$3 8: XLXN_307/XLXN_307_D2 15: accu_out<1> 2: $OpTx$FX_DC$7 9: accu_in<0> 16: accu_out<2> 3: TASTER_RES 10: accu_in<1> 17: accu_out<3> 4: XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D 11: accu_in<2> 18: accu_out<4> 5: XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D 12: accu_in<4> 19: cnt<0> 6: XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2 13: accu_in<5>/accu_in<5>_CE 20: d2/d2_D2 7: XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2 14: accu_out<0> 21: d3/d3_D2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs $OpTx$FX_DC$11 .X......XXX............................. 4 G X......X...........XX................... 4 accu_in<0> .XX.....X...X........................... 4 XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2 ........XX...XX......................... 4 D X......X...........XX................... 4 XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2 ......X...X....X........................ 3 XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2 ...XXX.....X....XX...................... 6 C X......X...........XX................... 4 accu_out<3> ..X.XX......X.....X..................... 5 accu_out<2> ..X...X...X.X.....X..................... 5 F X......X...........XX................... 4 accu_in<2> .XX.....XXX.X........................... 6 accu_in<1> .XX.....XX..X........................... 5 E X......X...........XX................... 4 B X......X...........XX................... 4 accu_out<4> ..XXXX......X...X.X..................... 7 A X......X...........XX................... 4 accu_out<1> ..X.....XX..XXX...X..................... 7 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$11 <= (accu_in(0) AND accu_in(1) AND accu_in(2) AND $OpTx$FX_DC$7); $OpTx$FX_DC$12 <= (cnt(0) AND cnt(1) AND cnt(2) AND $OpTx$FX_DC$6); $OpTx$FX_DC$3 <= ((accu_in(0) AND EN_DISP(0) AND LED(1)) OR (accu_out(0) AND NOT EN_DISP(0) AND NOT LED(1)) OR (cnt(0) AND NOT EN_DISP(0) AND LED(1)) OR (accu_out(4) AND EN_DISP(0) AND NOT LED(1))); $OpTx$FX_DC$6 <= (NOT TASTER_U AND XLXN_204 AND LED(0) AND LED(1)); $OpTx$FX_DC$7 <= (NOT TASTER_U AND XLXN_204 AND NOT LED(0) AND LED(1)); $OpTx$FX_DC$9 <= (cnt(0) AND cnt(1) AND $OpTx$FX_DC$6); A <= ((NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND NOT $OpTx$FX_DC$3) OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND d3/d3_D2) OR (XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND $OpTx$FX_DC$3 AND d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); B <= ((XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND NOT $OpTx$FX_DC$3) OR (XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND d3/d3_D2) OR (XLXN_307/XLXN_307_D2 AND $OpTx$FX_DC$3 AND d3/d3_D2) OR (d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); C <= ((XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND d3/d3_D2) OR (d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND d3/d3_D2) OR (XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND NOT d3/d3_D2)); D <= ((XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND $OpTx$FX_DC$3) OR (XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND NOT d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); E <= (($OpTx$FX_DC$3 AND NOT d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND NOT d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND $OpTx$FX_DC$3)); FTCPE_EN_DISP0: FTCPE port map (EN_DISP(0),'1',CLK_SLOW,NOT TASTER_RES,'0'); FDCPE_EN_DISP1: FDCPE port map (EN_DISP(1),EN_DISP(0),CLK_SLOW,'0',NOT TASTER_RES); F <= ((XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND NOT d3/d3_D2) OR (XLXN_307/XLXN_307_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND d3/d3_D2) OR (NOT d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); G <= ((NOT XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND NOT d3/d3_D2) OR (XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); FTCPE_LED0: FTCPE port map (LED(0),LED_T(0),CLK_SLOW,'0',NOT TASTER_RES); LED_T(0) <= (NOT TASTER_R AND XLXN_163 AND NOT accu_in(5)/accu_in(5)_CE); FTCPE_LED1: FTCPE port map (LED(1),LED_T(1),CLK_SLOW,'0',NOT TASTER_RES); LED_T(1) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(0) AND LED(1)); XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D <= accu_in(4) XOR XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D <= accu_out(4); XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D <= accu_in(7) XOR XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D <= accu_out(7); XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2 <= ((accu_in(4) AND accu_out(4)) OR (accu_out(3) AND XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D AND NOT XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D) OR (XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D AND XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D AND XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2)); XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2 <= ((accu_in(5) AND accu_out(5)) OR (accu_in(5) AND XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2) OR (accu_out(5) AND XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2)); XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D <= accu_in(3) XOR XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D <= accu_out(3); XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2 <= ((accu_in(2) AND accu_out(2)) OR (accu_in(2) AND XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2) OR (accu_out(2) AND XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2)); XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2 <= ((accu_in(1) AND accu_out(1)) OR (accu_in(0) AND accu_in(1) AND accu_out(0)) OR (accu_in(0) AND accu_out(0) AND accu_out(1))); FDCPE_XLXN_163: FDCPE port map (XLXN_163,TASTER_R,CLK_SLOW,'0','0'); FDCPE_XLXN_204: FDCPE port map (XLXN_204,TASTER_U,CLK_SLOW,'0','0'); XLXN_307/XLXN_307_D2 <= ((accu_in(1) AND EN_DISP(0) AND LED(1)) OR (accu_out(1) AND NOT EN_DISP(0) AND NOT LED(1)) OR (cnt(1) AND NOT EN_DISP(0) AND LED(1)) OR (accu_out(5) AND EN_DISP(0) AND NOT LED(1))); FDCPE_accu_in0: FDCPE port map (accu_in(0),accu_in_D(0),CLK_SLOW,NOT TASTER_RES,'0'); accu_in_D(0) <= ((NOT accu_in(0) AND $OpTx$FX_DC$7) OR (accu_in(0) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$7)); FTCPE_accu_in1: FTCPE port map (accu_in(1),accu_in_T(1),CLK_SLOW,NOT TASTER_RES,'0'); accu_in_T(1) <= ((accu_in(0) AND NOT accu_in(1) AND accu_in(5)/accu_in(5)_CE) OR (accu_in(0) AND NOT accu_in(5)/accu_in(5)_CE AND $OpTx$FX_DC$7) OR (NOT accu_in(0) AND accu_in(1) AND accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$7)); FTCPE_accu_in2: FTCPE port map (accu_in(2),accu_in_T(2),CLK_SLOW,NOT TASTER_RES,'0'); accu_in_T(2) <= ((accu_in(1) AND NOT accu_in(2) AND accu_in(5)/accu_in(5)_CE) OR (NOT accu_in(1) AND accu_in(2) AND accu_in(5)/accu_in(5)_CE) OR (accu_in(0) AND accu_in(1) AND NOT accu_in(5)/accu_in(5)_CE AND $OpTx$FX_DC$7)); FDCPE_accu_in3: FDCPE port map (accu_in(3),accu_in_D(3),CLK_SLOW,NOT TASTER_RES,'0'); accu_in_D(3) <= ((accu_in(2) AND accu_in(5)/accu_in(5)_CE) OR (NOT accu_in(3) AND $OpTx$FX_DC$11) OR (accu_in(3) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$11)); FDCPE_accu_in4: FDCPE port map (accu_in(4),accu_in(3),CLK_SLOW,NOT TASTER_RES,'0',accu_in_CE(4)); accu_in_CE(4) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); accu_in(5)/accu_in(5)_CE <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); FDCPE_accu_in5: FDCPE port map (accu_in(5),accu_in(4),CLK_SLOW,NOT TASTER_RES,'0',accu_in_CE(5)); accu_in_CE(5) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); FDCPE_accu_in6: FDCPE port map (accu_in(6),accu_in(5),CLK_SLOW,NOT TASTER_RES,'0',accu_in_CE(6)); accu_in_CE(6) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); FDCPE_accu_in7: FDCPE port map (accu_in(7),accu_in(6),CLK_SLOW,NOT TASTER_RES,'0',accu_in_CE(7)); accu_in_CE(7) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); FTCPE_accu_out0: FTCPE port map (accu_out(0),accu_in(0),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(0)); accu_out_CE(0) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); FDCPE_accu_out1: FDCPE port map (accu_out(1),accu_out_D(1),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(1)); accu_out_D(1) <= (accu_in(0) AND accu_out(0)) XOR accu_out_D(1) <= ((accu_in(1) AND NOT accu_out(1)) OR (NOT accu_in(1) AND accu_out(1))); accu_out_CE(1) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); FTCPE_accu_out2: FTCPE port map (accu_out(2),accu_out_T(2),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(2)); accu_out_T(2) <= ((accu_in(2) AND XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2) OR (NOT accu_in(2) AND NOT XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2)); accu_out_CE(2) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); FDCPE_accu_out3: FDCPE port map (accu_out(3),accu_out_D(3),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(3)); accu_out_D(3) <= XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D XOR accu_out_D(3) <= XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2; accu_out_CE(3) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); FDCPE_accu_out4: FDCPE port map (accu_out(4),accu_out_D(4),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(4)); accu_out_D(4) <= XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D XOR accu_out_D(4) <= ((NOT accu_out(3) AND NOT XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D) OR (XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D AND NOT XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2)); accu_out_CE(4) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); FTCPE_accu_out5: FTCPE port map (accu_out(5),accu_out_T(5),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(5)); accu_out_T(5) <= ((accu_in(5) AND XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2) OR (NOT accu_in(5) AND NOT XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2)); accu_out_CE(5) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); FTCPE_accu_out6: FTCPE port map (accu_out(6),accu_out_T(6),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(6)); accu_out_T(6) <= ((accu_in(6) AND XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2) OR (NOT accu_in(6) AND NOT XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2)); accu_out_CE(6) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); FDCPE_accu_out7: FDCPE port map (accu_out(7),accu_out_D(7),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(7)); accu_out_D(7) <= XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D XOR accu_out_D(7) <= ((EXP6_.EXP) OR (accu_in(6) AND XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2) OR (accu_out(6) AND XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2)); accu_out_CE(7) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); FDCPE_cnt0: FDCPE port map (cnt(0),cnt_D(0),CLK_SLOW,NOT TASTER_RES,'0'); cnt_D(0) <= ((NOT cnt(0) AND $OpTx$FX_DC$6) OR (cnt(1) AND accu_in(5)/accu_in(5)_CE) OR (cnt(0) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$6)); FDCPE_cnt1: FDCPE port map (cnt(1),cnt_D(1),CLK_SLOW,NOT TASTER_RES,'0'); cnt_D(1) <= ((cnt(2) AND accu_in(5)/accu_in(5)_CE) OR (cnt(1) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$9) OR (cnt(0) AND NOT cnt(1) AND LED(1) AND accu_in(5)/accu_in(5)_CE) OR (cnt(0) AND NOT cnt(1) AND LED(1) AND $OpTx$FX_DC$6)); FDCPE_cnt2: FDCPE port map (cnt(2),cnt_D(2),CLK_SLOW,NOT TASTER_RES,'0'); cnt_D(2) <= ((NOT cnt(2) AND $OpTx$FX_DC$9) OR (cnt(3) AND accu_in(5)/accu_in(5)_CE) OR (cnt(2) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$9)); FDCPE_cnt3: FDCPE port map (cnt(3),cnt_D(3),CLK_SLOW,NOT TASTER_RES,'0'); cnt_D(3) <= ((NOT cnt(3) AND $OpTx$FX_DC$12) OR (cnt(3) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$12)); d2/d2_D2 <= ((accu_in(2) AND EN_DISP(0) AND LED(1)) OR (accu_out(2) AND NOT EN_DISP(0) AND NOT LED(1)) OR (cnt(2) AND NOT EN_DISP(0) AND LED(1)) OR (accu_out(6) AND EN_DISP(0) AND NOT LED(1))); d3/d3_D2 <= ((accu_in(3) AND EN_DISP(0) AND LED(1)) OR (accu_out(3) AND NOT EN_DISP(0) AND NOT LED(1)) OR (cnt(3) AND NOT EN_DISP(0) AND LED(1)) OR (accu_out(7) AND EN_DISP(0) AND NOT LED(1))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-10-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572XL-10-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 LED<0> 23 GND 2 LED<1> 24 TIE 3 TIE 25 G 4 TIE 26 D 5 TIE 27 C 6 CLK_SLOW 28 F 7 TIE 29 E 8 TIE 30 TDO 9 TIE 31 GND 10 GND 32 VCC 11 TIE 33 B 12 TIE 34 A 13 TIE 35 TIE 14 TIE 36 EN_DISP<1> 15 TDI 37 EN_DISP<0> 16 TMS 38 TASTER_RES 17 TCK 39 TASTER_R 18 TIE 40 TIE 19 TIE 41 VCC 20 TIE 42 TIE 21 VCC 43 TASTER_U 22 TIE 44 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-PC44 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : FLOAT Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 90